With the widespread acceptance of personal computers in today's society, there is a constant need to reliably and expediently transfer large blocks of data among various component of the system. Networked personal computers (PC) have a constant need to receive and transmit large blocks of data among each other. Furthermore, the need for transferring large blocks of data is specially important in the increasingly popular client/server information handling environments. In such environments, a plurality of client work stations are networked and coupled to one or more server system, thus, allowing the client stations to share system resources, such as, files, printers, and applications. As a result, server systems are often required to transfer very large blocks of data from storage devices to client stations. In order to insure data integrity, it is customary to generate a status signal upon completion of data block transfers indicating transfer error conditions, if any.
Generally, data transfer form one system to another is handled through a local interface controller which is coupled to a host system unit via an Input/output (I/O) expansion bus. The interface controller may be a storage device interface, such as a Small Computer System Interface (SCSI) controller, or a communication interface such as an Ethernet or Token Ring Local Area Network Controller (LAN). Some I/O expansion bus protocols allow an interface controller to take control of the bus and transfer data to and from the host unit. Such interface controllers are known as bus masters and operate with I/O buses supporting bus mastering protocols. Two exemplary I/O expansion buses supporting bus mastering protocols are Peripheral Component Interconnect (PCI) bus and MicroChannel I/O bus.
Over the years various techniques have been devised for transferring data to and from a memory device efficiently. Direct memory access (DMA) technique has been widely used to transfer large blocks of consecutive data from a direct access storage device (DASD) to and from system memory. In a computer system with DMA capability, CPU is relieved of the overhead involved in transferring large amounts of data by transmitting only a starting address, and block count to a DMA controller. The system CPU simply programs the DMA controller with the starting address and the byte count to perform the specified DMA transfer. The DMA controller, which may be implemented as a state machine, receives and stores within its internal registers the starting address information and the block count transmitted by the CPU. Thereafter, depending on data direction signaled by the CPU, the DMA controller sequentially transfers the data between the system memory and a local interface controller over the I/O expansion bus. Upon completion of each data transfer, the DMA controller generates a signal informing the CPU of completion of the data transfer as well as a status signal indicating whether any transfer error conditions occurred during the DMA transfer. Depending on a transfer error condition and controlling software, the CPU may retry the DMA cycle.
Therefore, some systems utilize a command transfer queuing technique to queue data transfer status information of data blocks thus allowing a CPU to appropriately time servicing data block transfers. One such method titled "SYSTEM FOR ASYNCHRONOUSLY DELIVERING SELF-DESCRIBING CONTROL ELEMENTS WITH A PIPE INTERFACE HAVING DISTRIBUTED SHARED MEMORY" is disclosed in the U.S. Pat. No. 5,325,492, issued on Jun. 28, 1994 and assigned to the assignee of the present invention.
However, with the advent of local interface controllers capable of performing local mastering there is also a need to reduce command block transfer overhead on the local processing side in order to increase data transfer throughput between host and local processing sides.
Typically a local interface controller has a series of registers which when loaded interrupt the local processing unit signaling pendency of a command. The command can be located within the registers, where it can be directly DMAed into the local memory by the local processing unit from the system memory. Alternatively, a host processing unit can create the command blocks and place them in a queue. Upon completion, the host processing unit can interrupt the local processing unit that one or more commands have been place in the queue. Upon receipt of such interrupt, the local processing unit is prompted to service that interrupt and process the command block.
Conventional, methods of transferring command blocks however require the host processing unit and the local processing unit to interact with each other. In addition to interrupting the local processor, such interaction requires existence of some type of synchronous or asynchronous communication, e.g. hand shaking, between the host processing unit and the local processing unit which may significantly increase overhead associated with transferring command blocks to the local processing side.
Furthermore, when interrupting the local processing unit, it is required to assign the highest priority to such interrupt to prevent wasting valuable host processing unit cycles.
Therefore, there is a need for a more efficient transfer of command blocks from the host processing side to the local processing side.